1. Field of the Invention
The present invention relates to a semiconductor device and an EEPROM emulation method using the semiconductor device, and in particular relates to a semiconductor device with a built-in flash memory and an EEPROM emulation method using the semiconductor device.
2. Description of Related Art
In order to rewrite and store data, the EEPROM (Electrically Erasable Programmable Read Only Memory) has been used as an externally attached device. For the same purpose, the flash memory is used more frequently today, which can be integrated in semiconductor devices such as microcomputers and can be handled easier than the EEPROM. To be more specific, a flash memory incorporated in a semiconductor device such as a microcomputer is used to emulate the EEPROM so as to rewrite and store data.
In relation to the above technique, for reference, the Patent Document 1 (Japanese Patent Application Publication JP-P2005-92659A) discloses a control device to write/read data. FIG. 1 is a block diagram to explain the configuration of a data writing/reading control device 10 according to the reference technique.
The data writing/reading control device 10 is provided with a flash memory 11, a CPU 12 and a ROM 13. The CPU 12 is connected to the flash memory 11 and the ROM 13 in the data writing/reading control device 10.
Here, the memory is divided into a plurality of blocks. When data is written in one of the plurality of the blocks, writing means is used to compare a free region capacity in the block and an amount of data to be written. If the amount of data to be written is larger, the writing means erases entire data written in the block, followed by writing data sequentially from the head or tail of the block. If the amount of data to be written is smaller, the writing means writes data sequentially from the region next to the region in which data is written in the block. When data is read from the block, the reading means is used to search for the region in which data is written lastly from the head or tail of the block sequentially so as to read data written in the region.
As a further reference technique, Patent Document 2 (Japanese Patent Application Publication JP-P2006-260468A) discloses a semiconductor device. FIG. 2 is a block diagram to explain the configuration of the semiconductor device 20 according to the reference technique.
The semiconductor device 20 is provided with a CPU 21, a flash memory 22, a flash controller 25, a RAM 26, and a peripheral macro 27. The flash memory 22 includes a program area 23 and an EEPROM substitution area 24.
The CPU 21 is connected to the program area 23 and the EEPROM substitution area 24 in the flash memory 22, the flash controller 25, the RAM 26 and the peripheral macro 27. The flash controller 25 is connected to the EEPROM substitution area 24 in the flash memory 22 and the RAM 26.
The program area 23 is used to store a flash operation program. The EEPROM substitution area 24 is used to store various kinds of data. From the program area 23, the CPU 21 reads the flash operation program which is executed to control the flash controller 25. The flash controller 25 updates data in the EEPROM substitution area 24 in accordance with a control performed by the CPU 21.
FIG. 3 is a schematic diagram to explain a further detailed configuration of the flash memory 22 in FIG. 2.
A flash memory 30 includes a data length storage area 31 and a data storage region 32. The flash memory 30 in FIG. 3 corresponds to the flash memory 22 in FIG. 2.
The data storage region 32 includes a plurality of sections 32a to 32g. A part of the plurality of the sections 32a to 32g in FIG. 3 corresponds to the data length storage area 23 in FIG. 2 and the remaining parts thereof correspond to the data storage region 24 in FIG. 2.
The EEPROM substitution area 24 uses a part of the flash memory 30 as the data length storage area 31 and the data storage region 32. Data updating by an EEPROM emulation function is realized by additionally writing data while updating an address in the data storage region 32.
Next, explanation will be made for a case in which, for example, a block Bm included in the data storage region 32 is brought into a data full state due to additional writing. In this case, a block subjected to write data is changed to a next block which is a block Bm+1 in order to maintain data updating by EEPROM emulation.
A data holding period in the block Bm is applied to while whose starting point is at the timing of the writing in the section 32a which is an initial data writing in that block. Note that, also for a data holding period disclosed in the Patent Document 1, the timing at which data is written initially in a block subjected to write data is used as a starting point.
Next, the principle of the operation of the general flash memory is described. FIGS. 4A and 4B are cross-sectional views to explain a configuration of an MOS transistor which is used as a flash memory. FIG. 4A is a cross-sectional view to explain an initial state in the flash memory. FIG. 4B is a cross-sectional view to explain a written state in the flash memory.
The MOS transistor is provided with a control gate 41a or 41b, a floating gate 42a or 42b, a source 43a or 43b, and a drain 44a or 44b. In other words, the MOS transistor includes a two-layer polycrystalline silicon gate which is made of the floating gate 42a or 42b and the control gate 41a or 41b. 
The MOS transistor in the initial state as shown in FIG. 4A does not have an electric charge in the floating gate. In contrast, the MOS transistor in the written state as shown in FIG. 4B has electrons in the floating gate.
FIGS. 5A and 5B are diagrams to explain the relationship between a voltage applied to a control gate and a current flowing as a result thereof in the MOS transistor used as a flash memory. FIG. 5A is a schematic diagram of the MOS transistor used as a flash memory. FIG. 5B is a graph to explain a change in the relationship between the voltage and the current under the initial state and the written state.
As shown in FIG. 5A, if a voltage VCG is applied to a control gate 51 with a voltage VD being applied to a drain 53 and a voltage VS (=0V) being applied to a source 52, a current ID is made to flow from the drain 53 to the source 52. The drain voltage VD is assumed to be constant.
In the graph of FIG. 5B, the lateral axis indicates the voltage VCG applied to the control gate 51 and the vertical axis indicates the current ID. Here, the first graph 55 shows an initial state and the second graph 56 shows a written state. In this example, the current ID starts flowing when the voltage VCG applied to the control gate 51 exceeds 1V in the initial state 55 without electrons in a floating gate. In other words, a threshold voltage is 1V in the initial state.
Next, a case is explained in which the voltage VCG is applied to the control gate 51 in the written state 56 with electrons in the floating gate. In this case, the current ID is prevented from flowing due to electrons in the floating gate when the voltage VCG is low and finally starts flowing when the voltage VCG exceeds 6V.
Accordingly, the MOS transistor can be used as a semiconductor nonvolatile memory with 1 bit by determining the initial state 55 as “1” and the written state 56 as “0”.
Next, operations to read, erase and write data in the semiconductor nonvolatile memory will be explained.
First of all, as explained above, as operation to read data, whether a bit is “0” or “1” can be read by determining whether or not the current ID is made to flow on a data line, namely, between the drain 53 and the source 52.
Next, as an operation to erase data, electrons can be extracted from the floating gate by applying a positive voltage to the source and the drain. That is, a bit can be turned into “1”.
Lastly, as an operation to write data, an erased state is realized in advance as a prerequisite.
That is, immediately before an operation to write data, there is nothing to execute when “1” is written because a bit is already corresponding to “1”. Only when “0” is written, a positive voltage is applied to the control gate 51 so as to inject electrons to the floating gate before reaching a threshold range in which a bit is determined to “0”.